VHDL One Hour Update 
January 15, 2007
Noon, E215
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References:
S. Brown and Z. Vranesic, Fundamentals of Digital Logic with VHDL Design, Second Edition, Mc Graw Hill, Inc.

K. Skahill, VHDL for Programmable Logic, Addison Wesley

http://en.wikipedia.org/wiki/VHDL

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VHDL, or VHSIC Hardware Description Language, was originally developed in the 1970's 
in a program funded by the US Department of Defense.  MilStd454, 
IEEE standards 1076 and 1164 were developed to standardize VHDL.  
VHDL is an industry standard for description, modeling and synthesis of digital circuits and systems.

A simple example of VHDL code follows this format:
1. declare inputs and outputs
2. declare the architecture of the system

VHDL has built-in support for the Boolean operators:
AND,OR,NOT,NAND,NOR,XOR, XNOR

After the ARCHITECTURE specification, the BEGIN keyword signals the start of the logical specifications.
The VHDL signal assignment operator is <=
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The following is a really small example:

f[a,b,c] = [ab] + [b'c]
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ENTITY example IS
    PORT (a,b,c  :IN   BIT;
          f      :OUT  BIT);
END example;

ARCHITECTURE LogicFunction OF example IS
BEGIN
    f<=(a AND b) OR (NOT b and c);
END LogicFunction;
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